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application note nov 2008 1 order number: 320005-04 conversion guide: numonyx tm strataflash ? embedded memory p33 (256-mbit, 256-mbit/256- mbit) 130nm to 65nm application note - 909 nov 2008
application note nov 2008 2 order number: 320005-04 legal lines and disclaimers information in this document is provided in connection with numo nyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical co ntrol or safety systems, or in nuclear f acility applications. numonyx b.v. may make changes to specifications an d product descriptions at any time, without notice. numonyx b.v. may have patents or pending patent applications, tr ademarks, copyrights, or other in tellectual property rights tha t relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implie d, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no respon sibility whatsoever for conf licts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to ob tain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting the numonyx website at http://www.numonyx.com . numonyx, the numonyx logo, and strataflash are trademarks or regist ered trademarks of numonyx b.v. or its subsidiaries in other countries. *other names and brands may be claimed as the property of others. copyright ? 2008, numonyx, b.v., all rights reserved.
application note nov 2008 3 order number: 320005-04 conversion guide: p33 130nm to 65nm contents 1.0 introduction .............................................................................................................. 5 2.0 device overview ........................................................................................................ 5 2.1 p33 130nm device .............................................................................................. 5 2.2 p33 65nm device ................................................................................................ 5 2.3 p33 130nm and 65nm features comparison ........................................................... 6 3.0 device packaging and ballout .................................................................................... 7 3.1 easy bga ballout................................................................................................. 7 3.2 tsop pinout ....................................................................................................... 8 4.0 hardware design considerations ............................................................................... 9 4.1 ac read specifications ......................................................................................... 9 4.2 ac write/erase specifications ......................... ...................................................... 9 4.3 dc current specification .................................................................................... 10 5.0 flash software design considerations ..................................................................... 11 5.1 device identification .......................................................................................... 11 5.2 read configuration register (rcr) .................. .................................................... 11 5.3 blank check ..................................................................................................... 12 5.4 device commands............................................................................................. 13 5.5 wait state comparison ..................................................................................... 13 5.5.1 wait state p33 65nm............................................................................. 13 5.5.2 wait state p33 130nm ........................................................................... 14 5.6 cfi differences ................................................................................................. 15 5.6.1 cfi revision ........................................................................................... 15 5.6.2 time-out changes................................................................................... 15 5.7 performance improvements in p33 65nm ............................................................. 16 6.0 conversion considerations ...................................................................................... 17 a additional information ............................................................................................ 17
conversion guide: p33 130nm to 65nm application note nov 2008 4 order number: 320005-04 revision history date of revision revision description may 2008 001 initial release. july 2008 02 removed buffer programming difference; added in its place section 5.7, ?perfor- mance improvements in p33 65nm? on page 16 . sep 2008 03 updated axcell trademark removed 64m related contents. nov 2008 04 returned to strataflashl trademark removed 128m related contents clarify package options for each density align address to start from a1 remove numonyx confidential remove enhanced configuration register command
application note sep 2008 5 order number: 320005-04 conversion guide: p33 130nm to 65nm 1.0 introduction this application note describes the migration from the numonyx tm strataflash ? embedded memory (p33-130nm) device to the numonyx tm strataflash ? embedded memory (p33-65nm) device. note: unless otherwise indicated, throughout the rest of this document, the numonyx tm strataflash ? embedded memory (p33-130nm) device is referred to as the p33 130nm device and the numonyx tm strataflash ? embedded memory (p33-65nm) device is referred to as the p33 65nm device. this document was written based on device information available at the time. any changes in specifications to either device mi ght not be reflected in this document. refer to the appropriate documents or sales personnel for the current product information before finalizing any design. 2.0 device overview the following sections provide a brief overvi ew of the feature differences between the p33 130nm and the p33 65nm devices. 2.1 p33 130nm device the p33 130nm device features 64-mbit through 512-mbit densities and ac/dc specifications for 52mhz operation. other features include high performance synchronous-burst read, buffered enhanced factory programming (befp) with a 32- word buffer, and an expanded otp register space. packaging options include industry- standard easy bga, tsop and quad+ packages. 2.2 p33 65nm device the p33 65nm device features 64-mbi t through 2-gbit densities and ac/dc specifications for 52 mhz operation. this document covers specially 256-mbit and 512- mbit (256m/256m) product information. ot her features include high performance synchronous-burst read, buffered enhanced factory programming (befp) with a 512- word buffer, and an expanded otp register space. the p33 65nm device also features enhanced protection via a password access feature, which allows users to protect write access to the pre-defined blocks. please contact the numonyx sales for further details concerning password access. packaging opti ons include industry-standard easy bga and tsop packages.
conversion guide: p33 130nm to 65nm application note sep 2008 6 order number: 320005-04 2.3 p33 130nm and 65nm features comparison note: this document doesn?t cover 64-mbit and 128-mbit die info rmation. please refer to numonyx local sales for detail. table 1: p33 130nm and 65nm feature comparison features / specifications p33 130nm p33 65nm available densities (monolithic) 64 mbit yes yes* 128 mbit yes yes* 256 mbit yes yes available densities (stack) 512 mbit yes yes performance speed 52 mhz 52 mhz initial access time (easy bga) 85 ns 95 ns initial access time (tsop) 95 ns 105 ns block architecture parameter blocks four: 32-kbyte four: 32-kbyte main blocks 128-kbyte 128-kbyte 16-bit data bus yes yes operating voltage logic core (v cc ) 2.3 v to 3.6 v 2.3 v to 3.6 v i/o (v ccq ) 2.3 v to 3.6 v 2.3 v to 3.6 v features otp register space 128-bits + 2 kbits 128-bits + 2 kbits flexible block locking yes yes buffered enhanced factor y program 32-word buffer 512-word buffer password access no yes blank check no yes reliability operating temperature ?40 c to +85 c ?40 c to +85 c cycles 100,000 100,000
application note sep 2008 7 order number: 320005-04 conversion guide: p33 130nm to 65nm 3.0 device packaging and ballout the following section provides a brief overvi ew of the package and ballout differences between the p33 130nm and p33 65nm devices. note: for 256m/256m stack tsop migration options, please cont act your local numonyx local sales representative. 3.1 easy bga ballout the easy bga ballout is available for both p33 130nm and p33 65nm products. ball pitch of the easy bga ballout is 1.0 mm. th e package has an 8 x 8 active-ball matrix. table 2: package comparison features / specifications p33 130nm p33 65nm monolithic densities easy bga yes yes tsop yes yes quad+ (scsp) yes no stack densities easy bga yes yes tsop yes see note quad+ (scsp) yes no figure 1: 64-ball easy bg a ballout (256/512-mbit) 1 8 234 5 67 easy bga top view- ball side down easy bga bottom view- ball side up 1 8 2 3 4 5 6 7 h g f e d c b a h g f e d c a a2 vss a9 a14 ce# a19 rfu a25 rfu vss vcc dq13 vss dq7 a24 vss a3 a7 a10 a15 a12 a20 a21 wp# a4 a5 a11 vccq rst# a16 a17 vccq rfu dq8 dq1 dq9 dq4 dq3 dq15 clk rfu oe# dq0 dq10 dq12 dq11 wait adv# we# a23 rfu dq2 dq5 vccq dq14 dq6 a1 a6 a8 a13 vpp a18 a22 vcc a23 a4 a5 a11 vccq rst# a16 a17 vccq a1 a6 a8 a13 vpp a18 a22 vcc a3 a7 a10 a15 a12 a20 a21 wp# rfu dq8 dq1 dq9 dq4 dq3 dq15 clk rfu oe# dq0 dq10 dq12 dq11 wait adv# we# rfu dq2 dq5 vccq dq14 dq6 a2 vss a9 a14 ce# a19 rfu a25 rfu vss vcc dq13 vss dq7 a24 vss b
conversion guide: p33 130nm to 65nm application note sep 2008 8 order number: 320005-04 notes: 1. a1 is the least significant address bit. 2. a24 is valid for 256-mbit densities and above; otherwise, it is a no connect (nc). 3. a25 is valid for 512-mbit densities; otherwise, it is a no connect (nc). 3.2 tsop pinout the tsop pinout is available and compat ible for both p33 130nm and p33 65nm products. pin 13 on p33 130nm is connected to vcc. for p33 65nm this pin has no internal connection; it may be driven or left floated 1. a1 is the least significant address bit. 2. a24 is valid for 256-mbit densities; otherwise, it is a no connect (nc). 3. no internal connection on vcc pin 13; it may be driven or floated. for legacy designs, pin can be tied to vcc figure 2: 56-lead tsop pinout (256-mbit) numonyx ? p33 flash memory 56-lead tsop pinout 14 mm x 20 mm top view 1 3 4 2 5 7 8 6 9 11 12 10 13 15 16 14 17 19 20 18 21 23 24 22 25 27 28 26 56 54 53 55 52 50 49 51 48 46 45 47 44 42 41 43 40 38 37 39 36 34 33 35 32 30 29 31 a14 a13 a12 a10 a9 a11 a23 a21 vss a22 vcc wp# a20 we# a19 a8 a7 a18 a6 a4 a3 a5 a2 rfu vss a24 wait dq15 dq7 a17 dq14 dq13 dq5 dq6 dq12 adv# clk dq4 rst# a16 dq3 vpp dq10 vccq dq9 dq2 dq1 dq0 vcc dq8 oe# ce# a1 vss a15 dq11
application note sep 2008 9 order number: 320005-04 conversion guide: p33 130nm to 65nm 4.0 hardware design considerations the p33 130nm and p33 65nm flash memory devices provide reliable, two-bit-per-cell storage technology for embedded applications . they satisfy the need for more density in less space, with a high-speed interface. both flash devices feature asymmetrically- blocked architecture, buffered enhanced factory programming, and synchronous-burst read mode. the following sections discuss hardware design considerations when converting from the p33 130nm device to the p33 65nm device. 4.1 ac read specifications refer to the product datasheet for detailed list of all read timing specifications: ?numonyx tm strataflash ? embedded memory (p33-130nm) datasheet (314749) ?numonyx tm strataflash ? embedded memory (p33-65nm) datasheet (320003) 4.2 ac write/erase specifications note: refer to the product datasheet for detailed list of all write and erase timing specifications. ?numonyx tm strataflash ? embedded memory (p33-130nm) datasheet (314749) ?numonyx tm strataflash ? embedded memory (p33-65nm) datasheet (320003) table 3: key ac read specification comparison features / specifications p33 130nm p33 65nm performance clock frequency (max) 52 mhz 52 mhz asynchronous access (t avqv t vlqv t elqv ) easy bga: 85 ns easy bga: 95 ns tsop: 95 ns tsop: 105 ns asynch page access time (t apa ) 25 ns 25 ns clock-to-data burst access (t chqv ) 17 ns 17 ns burst data hold time (t chqx )3 ns3ns address and adv# setup time (t avch , t vlch ) 9 ns 9 ns ce# setup time (t elch ) 9 ns 9 ns rise/fall time (t fclk/lclk )3.0 ns3.0 ns clock high/low time (t ch/cl )5 ns5ns vcc power valid to rst# de-assertion (high) 60 us 300 us async page size 4 words 16 words synchronous burst length (word) 4-, 8-, 16-, and cont. 4-, 8-, 16- and cont. burst suspend mode yes yes
conversion guide: p33 130nm to 65nm application note sep 2008 10 order number: 320005-04 4.3 dc current specification the p33 65nm device consumes higher power than the p33 130nm device in standby mode under max condition. table 4: key ac write-erase specification comparison features / specifications p33 130nm p33 65nm program performance program buffer size 64 bytes 1024 bytes single word program time (typ/max) 90/200 s 150/456 s aligned 32-word buffere d program time (typ) 145 kbytes/s (v ppl ) 188 kbyte/s (v pph ) 364 kbytes/s aligned 64-word buffere d program time (typ) ? 593 kbytes/s aligned 128-word buffere d program time (typ) ? 941 kbytes/s aligned 256-word buffere d program time (typ) ? 1.29 mbytes/s aligned 512-word buffere d program time (typ) ? 1.46 mbytes/s befp environment requirement 25 c +/- 5 c 100 p/e cycles 30 c +/- 10 c 50 p/e cycles befp time 188kb/s 2.0mb/s erase performance erase time - 16kw param. block (typ/max) 0.4/2.5 s 0.8/4.0 s erase time - 64kw main block (typ/max) 0.8/4.0 s 0.8/4.0 s program/erase suspend latency (typ) 20 s 20 s blank check no yes table 5: key dc read specification comparison features / specifications p33 130nm p33 65nm dc current characteristics standby current (typ/max) 70/195 a (256-mbit) 65/210 a (256-mbit) continuous burst read current (max) 28 ma (52 mhz) 24 ma (52 mhz) program/erase current (typ/max) 35/50 ma 35/50 ma vpp factory program current (max) 22 ma less than 1 ma
application note sep 2008 11 order number: 320005-04 conversion guide: p33 130nm to 65nm 5.0 flash software design considerations the following sections discuss software design considerations when converting from the p33 130nm device to the p33 65nm device. 5.1 device identification the p33 130nm and p33 65nm flash devices have identical device identification codes. 5.2 read configuration register (rcr) read configurations for both the p33 130nm and p33 65nm devices are configured using the read configuration register (rcr ). for example, to place the device in synchronous burst-read mode, you set the read mode bit in the rcr. the p33 65nm rcr includes the following modifications to the rcr: ? latency count rcr[14:11] : an additional bit, rcr14, has been added to the p33 65nm device; rcr14 was reserved on p33 130nm. p33 65nm supports latency counts of 8, 9, 10, 11, 12, 13, 14, and 15. ?wait polarity rcr[10] : p33 130nm default setting high and p33 65nm default setting is low. ? data hold rcr[9] : p33 130nm supports 1-clock or 2-clock cycle data hold. rcr[9] is reserved for p33 65nm and supports a data hold of one cycle only. ?wait delay rcr[8] : same values for p33 130nm and p33-65nm. ? burst sequence rcr[7] : p33 130nm supports linear ?1? and intel ?0? burst order. p33 65nm supports linear ?0? only. setting p33 65nm to ?1? will not affect the burst order; the burst order will always be linear. ? clock edge rcr[6] : same values for p33 130nm and p33 65nm. ? reserved rcr[5:4] : same values for p33 130nm and p33 65nm. ?burst wrap rcr[3] : same values for p33 130nm and p33 65nm. ? burst length rcr[2:0] : same values for p33 130nm and p33 65nm. note: the differences are summarized in the table below. table 6: p33 device id codes code type address offset device density p33-130nm codes p33-65nm codes top bottom top bottom device identification 0x01 256 mbit 891f 8922 891f 8922
conversion guide: p33 130nm to 65nm application note sep 2008 12 order number: 320005-04 5.3 blank check blank check is used to confirm whether a main-array block is completely erased. a blank check operation is performed one block at a time, and cannot be used during program suspend or erase suspend. to use blank check, issue the blank check setup command then the confirm command. the addressed partition is automatically changed to read status register mode, which remains in effect until another read-mode command is issued. during a blank check operation, the status register indicates a bu sy status (sr7 = 0). upon completion, the status register indicates a ready status (sr7 = 1). the status register should be checked for any errors, and then cleared. if the blank check operation fails, which means the bloc k is not completely erased, the status register will indicate a blank check error (sr[7,5] = 1). table 7: read configuratio n register differences register field value p33 130nm p33 65nm latency count 1000 =code 8 1001 = code 9 1010 = code 10 1011 = code 11 1100 = code 12 na available wait polarity 0 =wait signal is active low 1 =wait signal is active high default high default low data hold 0 =data held for a 1-clock data cycle 1 =data held for a 2-clock data cycle available 1-clock cycle only burst sequence 0 =reserved 1 =linear intel burst order linear burst order linear burst order clock edge 0 = falling edge 1 = rising edge available available burst wrap 0 =wrap; burst accesses wrap within burst length set by bl[2:0] 1 =no wrap; burst accesses do not wrap within burst length available available burst length 001 =4-word burst 010 =8-word burst 011 =16-word burst 111 =continuous-word burst available available
application note sep 2008 13 order number: 320005-04 conversion guide: p33 130nm to 65nm 5.4 device commands the command set for the p33 65nm and p 33 130nm devices are fully compatible. however, the p33 65nm device includes new features such as the blank check operation and the enhanced configuration operation. command set operations are compared here: note: during buffered program command (e8h) sequ ence, if a read of the main array data needs to be performed during the loading of the program buffer, then a write to an address outside of cu rrent block will abort the buffer programming operation. issuing the read array comm and (ffh) will put the device into read array mode. after main array read operation has been completed, the buffer program operation must be restarted. 5.5 wait state comparison this section will compare the difference be tween the wait states on the p33 130nm and the p33 65nm. 5.5.1 wait state p33 65nm end of wordline (eowl) wait states can resu lt when the starting address of the burst operation is not aligned to a 16-word boundary; that is, a[3:0] of start address does not equal 0x0. figure 3, ?end of wordline timing diagram? on page 14 illustrates the end of wordline wait state(s), which occur af ter the first 16-word boundary is reached. the number of data words and the number of wait states for both p33 130nm and p33 65nm are summarized in table 9, ?end of wordline data and wait state comparison? on page 14 . table 8: command bus operations command p33 130nm code (setup/confirm) p33 65nm code (setup/confirm) read modes read array 00ffh 00ffh read status register 0070h 0070h clear status register 0050h 0050h read device information 0090h 0090h cfi query 0098h 0098h program/erase operations word program 0040h 0040h buffered program 00e8h/00d0h 00e8h/00d0h buffered enhanced factory program 0080h/00d0h 0080h/00d0h block erase 0020h/00d0h 0020h/00d0h program/erase suspend 00b0h 00b0h program/erase resume 00d0h 00d0h blank check n/a 00bch/00d0h security lock block 0060h/0001h 0060h/0001h unlock block 0060h/00d0h 0060h/00d0h lock down block 0060h/002fh 0060h/002fh password access n/a 00ebh registers program read configuration register 0060h/0003h 0060h/0003h program otp register 00c0h 00c0h
conversion guide: p33 130nm to 65nm application note sep 2008 14 order number: 320005-04 5.5.2 wait state p33 130nm after encountering an eowl situation, periodic wait states can occur in general as illustrated in figure 4, ?periodic wait state timing diagram? on page 15 . figure 10, ?periodic data and wait state comparison? on page 15 shows that p33 130nm has periodic wait states, but p33 65nm does not. figure 3: end of wordline timing diagram table 9: end of wordline data and wait state comparison latency count p33 130nm p33 65nm data states wait states data states wait states 1 not supported not supported not supported not supported 240 to 1 not supported not supported 340 to 2 16 0 to 2 440 to 3 16 0 to 3 540 to 4 16 0 to 4 640 to 5 16 0 to 5 740 to 6 16 0 to 6 8 not supported not supported 16 0 to 7 9 16 0 to 8 10 16 0 to 9 11 16 0 to 10 12 16 0 to 11 13 16 0 to 12 14 16 0 to 13 15 16 0 to 14 a[max:1] adv# oe# wait dq[15:0] data data data eowl clk latency count
application note sep 2008 15 order number: 320005-04 conversion guide: p33 130nm to 65nm 5.6 cfi differences p33 65nm has a different cfi revision. during adoption of numonyx or third party software, several differences must be taken into account. this section will describe the changes. 5.6.1 cfi revision the cfi minor revision sorted in offset (p+4)h remains as 5. cfi version 1.5 is supported in th e software provided by numonyx. 5.6.2 time-out changes all cfi time-out changes are listed in table 11, ?value changes? figure 4: periodic wait state timing diagram table 10: periodic data and wait state comparison latency count p33 130nm p33 65nm data states wait states data states wait states 1 not supported not supported not supported not supported 24 0 not supported not supported 34 0 16 0 44 0 16 0 54 1 16 0 64 2 16 0 74 3 16 0 8 not supported not supported 16 0 9 16 0 10 16 0 11 16 0 12 16 0 13 16 0 14 16 0 15 16 0 addr[ max :16] addr [15:0] data data data data periodic periodic latency count latency count clk a[max:16] adv# oe# d[ 15: 0] wait a [max :1] data
conversion guide: p33 130nm to 65nm application note sep 2008 16 order number: 320005-04 5.7 performance improv ements in p33 65nm the write performance can be increased on p33 65nm by using the 1024 byte/512 word buffer. if buffered programming is being done using the 16 word buffer (similar to 130nm devices), no software changes need to be implemented. to achieve maximum performance using the 1024 byte/ 512 word buffer on 65nm devices, the following considerations apply during software modifications: 1. use the full 1024 byte/ 512 word buffer 2. if 1024 byte/ 512 word buffer is being used, the programming addresses should be aligned in 512 word address boundaries. for example: start programming address is 000000h and end programming address is 0001ffh. please refer to figure 3. 3. if the addresses must be mis-aligned, they must be in chunks of 256 words. for example: start programming address to start programming address + 0000ffh (256 words). please refer to figure 3. the read performance can be improved by providing read page buffer up to 16 words (p+1dh). table 11: value changes num difference 130nm 65nm offset value offset values 1 ?n? such that typical max. buffer write time-out = 2 n -sec 20h 512 20h 1024 2 ?n? such that maximum buffer write time-out = 2 n times typical 24h 1024 24h 4096 3 ?n? such that maximum number of bytes in write buffer = 2 n 2ah 64 2ah 1024 4 page mode read capability bits 0?7 = ?n? such that 2n hex value represents the number of read-page bytes. see offset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. (p+1d)h 8 (p+1d)h 32 figure 5: main array representation 256 words 000000h 000200h 0003ffh main array representation 512 words 512 words 256 words 0001ffh 256 words 256 words ffffffh
application note sep 2008 17 order number: 320005-04 conversion guide: p33 130nm to 65nm 6.0 conversion considerations p33 65nm has a larger program buffer size to greatly improves the write performance. users should use appropriate program and read modes to take advantage of this improved performance. appendix a additional information order/document number document/tool 314749 numonyx tm strataflash ? embedded memory (p33-130nm) datasheet 320003 numonyx tm strataflash ? embedded memory (p33-65nm) datasheet note: contact your local numonyx or distribution sales office or visit numonyx?s world wide web home page at http:// www.numonyx.com for technical documentation, tools, and additional information.
conversion guide: p33 130nm to 65nm application note sep 2008 18 order number: 320005-04

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